Senior ASIC STA Engineer

2 days ago


Dombivli, Maharashtra, India beBeeEngineering Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Job Title

Synthesis and Static Timing Analysis - Staff Design Engineer/Design Manager

Location: Bangalore/Hyderabad/Ahmedabad/Noida

Summary

As a key member of our Soc digital design team, you will be at the heart of the Soc design effort interfacing with all disciplines to drive successful product development.

In this highly visible role, you will lead the synthesis, static timing, and DFT efforts for an advanced mixed signal chip, collaborating with a talented team to deliver integrated solutions in a growth industry.

Key Responsibilities Include
  • Full chip and block level timing closure ownership throughout the project cycle (RTL, synthesis, and physical implementation).
  • Development and maintenance of methodology and flows related to timing verification and closure.
  • Generation of block and full chip timing constraints.
  • Analysis of timing reports and utilization of scripting techniques to drive rapid insights and improve Eteros Technologies, Inc. timing closure.
  • Support for digital chip integration work and flows.

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