
Chief Verification Strategist
2 days ago
Job Overview
The successful candidate will be responsible for leading the development and implementation of verification environments for complex IPs, subsystems, and System-on-Chip (SOC) designs. This role requires a strong understanding of business requirements and functional specifications to create effective verification strategies.
Key Responsibilities:
- Develop and maintain Verification Environment Architecture documents to ensure consistency and efficiency in the verification process.
- Review and revise code to meet acceptance criteria, ensuring that it is stable, reliable, and meets the required standards.
- Design and implement unit, subsystem, and SOC level verification using System Verilog, UVM, and C code.
- Perform RTL simulations using Synopsys and Cadence simulators to identify and resolve simulation issues.
- Develop performance test plans and maintain them to ensure efficient testing and validation.
- Create transactors, monitors, and models for performance verification, including implementing monitoring, synchronization, reporting, and self-checking mechanisms.
- Provide full reports on performance metrics and bottlenecks to stakeholders, identifying areas for improvement.
- Track tickets and code releases using Bug Tracking tools and GIT to ensure seamless collaboration and version control.
- Perform UPF-based Power Aware simulations to optimize power consumption and reduce energy costs.
- Implement coding of Assertion and Functional Coverage bins in SVA, ensuring thorough coverage and accuracy.
- Closure of code and functional coverage to ensure 100% verification of design functionality.
- Prepare and conduct reviews of Verification Sign-off documents to ensure completeness and accuracy.
Requirements and Qualifications:
- Strong understanding of digital design principles, including HDL languages such as System Verilog and Verilog.
- Experience with verification methodologies, including constrained-random stimulus and formal verification.
- Proficiency in simulation tools, including Synopsys VCS and Cadence NCVC.
- Knowledge of performance analysis and optimization techniques, including timing closure and power management.
- Excellent communication and project management skills to lead cross-functional teams and manage multiple projects simultaneously.
Benefits:
- Competitive salary and benefits package.
- Opportunities for professional growth and career advancement.
- Collaborative and dynamic work environment.
What We Offer:
Our company is committed to providing a supportive and inclusive work environment that fosters creativity, innovation, and teamwork. We offer competitive salaries, comprehensive benefits, and opportunities for professional growth and development. If you are a motivated and talented individual who is passionate about verification engineering, we encourage you to apply for this exciting opportunity.
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