Technical Lead for Digital Technology Solutions
1 week ago
We are seeking an experienced Technical Lead to join our Central DFT methodology group. As a senior member of this team, you will be responsible for developing flows across all company departments and projects.
Key Responsibilities- Architect methodologies and flows for an integrated, RTL-centric 'shift left' DFT environment across company IPs, chiplets, and SoC designs.
- Develop automated verification test bench and sequence creation for DFT IP, architecting end-to-end verification solutions from static design checks, through formal and sequence-based verification.
- Build IP/block and SoC level scan insertion flows and script ATPG retargeting procedures, creating automated QoR checks for implementation quality control.
- Write static timing constraints, create waivers, and devise flows for bullet-proof timing checks.
- Hiring, training, and leading DFT engineers in daily tasks and activities to fulfill company roadmaps.
- You will report to the Head of Central DFT Team and mentor DFT engineers throughout the project lifecycle.
To succeed in this role, you will need:
- Proven technical and people management skills.
- A collaborative team player with an out-of-the-box mindset.
- Good understanding of Verilog/VHDL and System Verilog.
- Exposure to CAD and automation, with good exposure to using Perl techniques in creating generic codes, knowledge of TCL and Python.
- Extensive experience with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687), and BIST techniques (memory BIST, logic BIST, interconnect BISTs).
- Track record in integrating custom-made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs.
- Experience in SoC and IP/block level scan insertion and ATPG, simulation of zero-delay and SDF annotated test sequences.
- Experience in scripting/reviewing SCAN/MBIST timing constraints.
- Developing DFT rule bases and DFT-DRC checks with Spyglass are valuable additions.
The ideal candidate will have:
- A Bachelor's degree in engineering science, electrical and computer engineering, or computer science.
- 10+ years of experience in complex SoC designs in RTL, DFT, or FE capacity. Candidates with less experience may be considered for other senior technical roles.
- Vast experience with various DFT EDA tools from Tessent, SNPS, and Cadence.
- Experience in core wrapping, pattern retargeting & packetizing ATPG techniques. SSN knowledge.
Mulya Technologies offers a comprehensive benefits package that includes competitive compensation, restricted stock units, hybrid working models, provisions to pursue advanced education, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch and snacks facilities.
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