
Senior ASIC Circuit Designer
4 days ago
Job Opportunity
We are seeking experienced RTL Design Engineers and Design Verification Engineers to join our team in Bangalore.
Requirements for RTL Design Engineer:
- 5+ years of experience in designing ASIC circuits at the Register-Transfer Level
- Strong skills in Static Concurrency Checking, Lint checking, Synthesis, and RTL design verification
- Experience with tools such as Lint and Static Concurrency Checker
- Understanding of timing concepts and synthesis techniques
- Knowledge of AMBA protocols - AXI, AHB, APB, and SoC clocking/reset architecture is a plus
Requirements for Design Verification Engineer:
- 5-20 years of experience in design verification engineering
- IP verification using SystemVerilog/UVM
- SOC verification using C/SV
- Third-party Virtual IP integration
- Interconnect protocols: AHB, AXI, APB
- SOC interfaces: GPIO, SPI, I2C, UART (3+)
- High-speed serial interfaces: PCIe Gen 3/4 or USB or MIPI (7+)
- Memory interfaces: DDR or HBM I/O (10+)
- Coverage closure: code, functional, and toggle coverage
- Tools: Synopsys VCS or Cadence Incisive
- Technical documentation: testbench specification, test plan specification
- Foundry porting experience: technology library conversion related changes verification
Key Skills:
- RTL ASIC design
- Design verification
- Logic design
- IP design and integration
- AMBA protocols - AXI, AHB, APB
- SoC clocking/reset architecture
Preferred Qualifications:
- Experience with synthesis and timing concepts
- Knowledge of high-speed serial interfaces and memory interfaces
How to Apply:
Interested candidates, please share your updated CV or contact us via the provided information.
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