Senior ASIC Design Engineer

2 weeks ago


Bengaluru, Karnataka, India beBeePhysical Full time ₹ 18,20,655 - ₹ 25,46,086
Job Title: ASIC Engineer - Physical Design

About the Role:

This position offers an exciting opportunity to work as a skilled ASIC engineer specializing in physical design. As part of our dynamic team, you will be responsible for all aspects of Fullchip/Blocks Physical Design, including Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.

Key Responsibilities:

  • Responsible for leading complex designs from conception to delivery, ensuring timely completion and meeting quality standards.
  • Sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow.
  • Collaborate closely with the methodology team to resolve implementation challenges and provide valuable inputs to improve the Physical design flow.
  • Demonstrated expertise in design automation, with a strong understanding of Timing constraints, SI prevention, and Power reduction techniques.
  • Prior experience working with Synopsys/Cadence/Mentor place and route tools, delivering successful projects on 16nm and/or 7nm process nodes.
  • Proficient in Unix/TCL/Perl programming languages, with excellent communication and presentation skills, as well as strong interpersonal skills and problem-solving ability.

Requirements:

  • Minimum 4 years of experience in ASIC physical design, with a proven track record of successfully completing complex projects.
  • Strong experience with block implementation, extraction, timing, and full-chip designs, along with hands-on TCL/Perl development skills.

Preferred Qualifications:

  • Experience as a full-chip floorplanning, routing, or timing lead for large silicon projects, with a history of taping out complex chips on advanced process nodes.


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