High-Performance SoC Architecture Specialist

3 weeks ago


Pune, Maharashtra, India Mulya Technologies Full time
  • Job Role: Principal System-on-Chip Microarchitecture Designer
  • About Us: Mulya Technologies is a US-based well-funded product-based startup founded by highly respected Silicon Valley veterans with design centers in Santa Clara, California, and Hyderabad.
  • Job Description: We are seeking highly talented ASIC/RTL/Logic Design Engineers for various roles. The ideal candidate will have experience designing and integrating high-performance Arm, x86, or RISC-V SoCs, as well as prior experience with IP development and RTL integration of SoC components like interconnects, memory controllers, and IO controllers.
  • Responsibilities:
    • Work on designing and integrating high-performance System-on-Chip architectures.
    • Perform architectural exploration for power, performance, and area-efficient SoCs.
    • Develop microarchitecture specifications documents.
    • Coding in Verilog or System Verilog towards IP development, and integrating SoC RTL modules in building large systems.
    • Make external sourcing versus custom design decisions for various SoC modules.
    • Collaborate with the performance analysis team to design, correlate, and enhance performance metrics.
    • Collaborate with pre-silicon verification, emulation, and post-silicon validation to develop validation infrastructure and ensure design functionality.
    • Work with the physical design team in synthesis, place, and route planning, and ensuring the design meets area and frequency requirements.
  • Requirements:
    • Master's, PhD, or bachelor's degree in a relevant subject area.
    • Thorough knowledge of high-performance CPU, GPU, or heterogeneous compute systems.
    • Prior experience designing and integrating high-performance Arm, x86, or RISC-V SoCs.
    • Prior experience with IP development and RTL integration of SoC components.
    • Proficiency in Verilog or System Verilog coding.
    • Understanding of high-performance and low-power microarchitecture techniques and logic design principles.
    • Experience with front-end ASIC design EDA tools.


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