Senior Performance Modeling Engineer

2 weeks ago

Noida, Uttar Pradesh, India beBeePerformanceEngineer Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

We are looking for a skilled engineer to help develop performance models, perform architectural tradeoff analysis, and enable data-driven design decisions for next-generation DDR memory controller architectures.

Main Responsibilities:

  • Develop cycle-level performance models in SystemC or C++
  • Correlate performance models to match RTL configurations and traffic conditions
  • Work with Architects to understand feature requirements, architectural specifications, and implement in the model
  • Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
  • Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
  • Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Requirements:

  • Bachelor's/Master's degree in ECE, E&TC, CS or similar
  • 2-10 years of experience in hardware modeling, functional or performance
  • Strong coding skills in C++, SystemC, and Transaction Level Modeling (TLM)
  • Fundamental understanding of performance principles, Queuing Theory, throughput/latency tradeoffs

Additional Requirements:

  • Understanding of RTL-Verilog, SV, UVM, and experience analyzing waveforms
  • Understanding of memory protocols and timing DDR4, DDR5, LP4, LP5
  • Experience using performance simulators Memory Controller, NoC, CPU models
  • Coding in Python and familiarity with packages like Pandas, Matplotlib
  • Experience working with performance benchmarks SPEC, STREAM, etc
  • Concepts related to Quality of Service (QoS) and how memory controller can trade-off performance and latencies

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