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14 hours ago
Job Title: Architect of Memory Hierarchies
We are seeking a skilled memory architect to develop compilers layouts and Fast Cache instances layouts for our next generation Cores, achieving outstanding PPA.
The ideal candidate will have a strong understanding of CMOS Transistors, their behaviors, and basic knowledge of CMOS logic design and layout. You should also have an engineering demeanor and passion for Circuit layouts, as well as good interpersonal skills.
Key Responsibilities:- Create high-quality design rule-driven layouts for memory compilers and Fast Cache instances.
- Review schematics with engineering teams and propose changes based on layout implications.
- Explore possible floor planning options and propose improvements.
- Develop and maintain technical documentation for memory compiler and Fast Cache instance designs.
- Minimum 5 years of experience in SRAM/memory layouts creation and backend verifications, including EMIR analysis.
- Strong understanding of CMOS Transistors and their behaviors.
- Basic knowledge of CMOS logic design and layout.
- Engineering degree in Electronic Engineering or equivalent.
- Good interpersonal skills and ability to work effectively in a team environment.
Nice to Have Skills and Experience:
- Basic scripting languages (e.g., Perl).
- Experience working on Cadence or Synopsys flows.
If you have a passion for Circuit layouts and a strong background in memory architecture, we encourage you to apply for this exciting opportunity.
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