
Senior Design Engineering Specialist
1 day ago
We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have extensive knowledge of Cadence or Synopsys physical design tools, with expertise in scripting languages such as Perl or TCL.
The successful candidate will be able to perform top-level floor planning, placement, routing, timing optimization, SI aware routing, and timing analysis/closure tasks. They should also have experience working on designs at 65nm or lower node sizes, using advanced low power techniques such as voltage islands, power gating, and substrate bias.
Key Responsibilities:
• Provide technical guidance and mentoring to junior engineers.
• Interface with front-end ASIC teams to resolve issues.
• Low Power Design - use voltage islands, power gating, and substrate-bias techniques.
• Timing closure on DDR2/DDR3/PCIE interfaces.
Requirements:
• Excellent communication skills.
• Strong background in ASIC physical design: floor planning, placement and routing, extraction, IR drop analysis, timing and signal integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical design tools.
• Expertise in scripting languages such as Perl, TCL.
• Strong physical verification skill set.
• Static timing analysis in Primetime or Primetime-SI.
• Good written and oral communication skills, ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.
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