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Formal Verification Expert Lead

We are seeking an experienced Formal Verification expert to lead formal verification efforts for complex digital designs. As a senior Formal Verification expert, you will be responsible for developing and implementing formal verification strategies and test plans for single or multiple design blocks and IPs.

About the Role:
  • Develop comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality.
  • Prove design properties, identify bugs, and collaborate with design teams to improve micro-architectures and ensure design correctness.
  • Craft innovative solutions for verifying complex design architectures, including developing re-usable and optimized formal models and verification code bases.
Requirements:
  • Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.
  • 10+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques.
  • Expertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL.
  • Experience with industry-standard EDA formal tools.
  • Experience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC.