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1 week ago
As an experienced RTL to GDSII Engineer, you will play a key role in driving innovation through the development of high-quality designs.
Key Responsibilities:- Develop and maintain Design Compiler (DC) constraint files to optimize synthesis performance and ensure efficient design closure.
- Perform pre-timing synthesis on RTL designs to guarantee accurate timing analysis and minimize potential errors.
- Collaborate with cross-functional teams to execute pre-static timing analysis (pre-STA) and support physical design activities, achieving seamless design execution.
- A minimum of 5 years of experience in RTL to GDSII design flow, with a strong background in synthesis, static timing analysis (STA), and physical design processes.
- Hands-on expertise in writing DC constraint files to drive efficient synthesis and maximize design potential.
- Proven ability to debug and resolve complex design and timing issues, ensuring timely and cost-effective solutions.
- Opportunity to work with cutting-edge technologies and contribute to innovative design projects.
- Chance to collaborate with experienced engineers and develop skills in RTL to GDSII design flow.
- Professional growth and development opportunities in a dynamic and challenging environment.
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Digital Experience Specialist
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Circuit Design Specialist
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