
Senior Verification Engineer
2 weeks ago
Power Verification Expert
">The role of Power Verification Engineer involves end-to-end power verification of ASIC/SOC designs. This encompasses power-aware verification with UPF, verification of leakage, sleep, clock tree, and active use cases.
">- Power-aware verification with Unified Power Format (UPF)">
- Verification of leakage, sleep, clock tree, and active use cases">
- Clock and reset verification, including glitch, frequency, and specification compliance">
- Power switch coverage analysis">
Key Skills:
">- Digital Verification (DV) expertise in SystemVerilog and Universal Verification Methodology (UVM)">
- Strong RTL and Gate-Level Simulation (GLS) skills with PG netlist">
- Understanding of power intent and SoC clock/reset architecture">
- C programming language proficiency">
- Processor knowledge, with a preference for Digital Signal Processing (DSP) subsystems">
- Experience with Neural Network Engines (NNE) and performance verification methods">
Requirements for Debug Subsystem Verification:
">- End-to-end Debug Subsystem verification">
- RTL DV, GLS, coverage closure">
- Understanding of ARM CoreSight Debug Architecture">
- Collaboration with architecture and SW teams for debug requirements">
- Development of Verification Plan (VPlan)">
- Strong expertise in C, SV, and UVM">
Qualifications and Requirements:
">- 6 years of experience in verification engineering">
- Strong knowledge of SystemVerilog, UVM, and C programming languages">
- Experience with RTL, GLS, and PG netlist">
- Understanding of power intent and SoC clock/reset architecture">
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