Advanced System Designer

2 weeks ago

Hyderabad Secunderabad Telangana, India beBeeDesign Full time US$ 1,50,000 - US$ 2,00,000
Senior Design Engineer for Complex SoCs

This role is for a senior design engineer to contribute significantly in the synthesis and static timing analysis of complex Systems-on-Chips (SoCs). The ideal candidate will have extensive experience in timing closure, I/O constraint development for industry-standard protocols, and hands-on experience with advanced technology nodes.

Key Responsibilities:
  • Synthesis of Complex SoCs: Perform synthesis of complex SoCs at both block and top levels, ensuring optimal performance and power consumption.
  • Timing Constraints Development: Develop and write timing constraints for intricate designs, including those with multiple clocks and voltage domains.
  • Post-Layout Timing Closure: Lead post-layout timing closure for multiple tape-outs, handling timing ECOs and achieving STA signoff.
  • I/O Constraints Development: Develop I/O constraints for industry-standard protocols such as DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display, etc.
  • Formal Verification: Conduct formal verification (RTL-to-netlist and netlist-to-netlist) with DFT constraints.
Required Skills and Qualifications:
  • Expertise in Synthesis and STA: Strong understanding of synthesis and Static Timing Analysis (STA) techniques.
  • Proficiency in Writing Timing Constraints: Ability to write timing constraints for complex designs.
  • Hands-on Experience with Post-Layout Timing Closure: Practical experience with post-layout timing closure, including timing ECOs.
  • Expertise in I/O Constraint Development: Proficiency in developing I/O constraints for various industry-standard protocols.
  • Strong Knowledge of EDA Tools: Familiarity with Electronic Design Automation (EDA) tools such as RC, DC, PT, PTSI.
  • Good Understanding of VLSI Process and Device Characteristics: Knowledge of VLSI process and device characteristics.
  • Good Understanding of Deep Submicron Parasitic Effects and Crosstalk Effects: Awareness of deep submicron parasitic effects and crosstalk effects.
Qualifications:
  • Education: B.Tech. or M.Tech. with relevant experience in Synthesis, STA.
  • Experience: Hands-on experience working on technology nodes like 28nm, 20nm, 14nm, 10nm.

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