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2 weeks ago
This role entails overseeing the architecture of a verification environment from scratch, creating test plans and implementing a top-down DV flow in collaboration with design and architecture teams.
Main Responsibilities:
- Develop and implement a DV methodology, create comprehensive test plans, and execute them.
- Collaborate with design, architecture, system validation, and software teams to perform chip verification.
- Create DV testing plans, propose strategies, build test platforms, and ensure quality with coverage tools.
Key Qualifications:
- 10+ years of experience in building test environments from scratch, including specifications understanding, comprehensive test plan creation, top-level testbench architecting, and leading to coverage closure.
- Expertise with verification tools like Verilog, SystemVerilog, UVM, OVM, etc.
- Experience in standards-based verification like MIPI, USB3, Ethernet is preferred.
- Power-aware designs DV experience is a plus.
- A self-starter who can develop a verification strategy for new devices without legacy references.
- A motivated individual contributing towards exciting opportunities to build industry-first products.
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