Senior Verification Expert

17 hours ago

Kozhikode, Kerala, India beBeeVerification Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

As a senior design verification engineer, you will be instrumental in ensuring the quality and functionality of our advanced ASICs and SoCs. This position demands a strong foundation in verification methodologies and the ability to handle complex verification tasks.

You will be responsible for developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Your expertise in digital design principles, advanced verification methodologies, and best practices will enable you to drive the development and execution of comprehensive verification plans.

Key Responsibilities
  • Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification)
  • Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage and functional verification goals
  • Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis
  • Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution
  • Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team
  • Champion best practices for verification code quality and participate in code reviews
  • Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies
  • Provide technical leadership and contribute to the overall verification roadmap for the team
Qualifications and Requirements
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
  • 7-10 years of solid experience in Design Verification for ASICs or SoCs
  • In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
  • Proven ability to develop, debug, and optimize complex verification environments
  • Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)
  • Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)
  • Experience with formal verification tools and techniques is a plus
  • Excellent analytical and problem-solving skills with a meticulous attention to detail
  • Strong communication, collaboration, and leadership skills to effectively contribute and guide the team
Benefits
  • Competitive salary and benefits package commensurate with experience
  • Opportunity to work on leading-edge technologies and projects with a high impact
  • Collaborative and dynamic work environment that fosters continuous learning
  • Potential for professional development and career advancement

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