
Senior PCIe/CXL/IDE Engineering Professional
7 days ago
Our team seeks a skilled Principal RTL Engineer to develop and support our PCIe/CXL/IDE IP solution.
- Design and development of the PCIe/CXL/IDE IP solution RTL
- Collaboration with existing RTL, addition of new features
- Verification and validation of customer configurations
- Support for customers regarding design clean-up and adherence to LINT and CDC guidelines
Requirements:
- BE/BTech/ME/MTech in Electrical/Electronics/VLSI with experience as a design and verification engineer
- 8-16 years of core RTL Design experience using Verilog
- System Verilog expertise and UVM-based environment usage/debugging required
- PCIe/CXL/IDE experience necessary
- Prior experience in implementing complex protocols advantageous
Desirable Skills:
- Scripting knowledge beneficial
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