System Verification Specialist

5 days ago


Bengaluru, Karnataka, India beBeeVerification Full time ₹ 1,80,00,000 - ₹ 2,52,00,000

We are seeking a highly skilled verification professional to join our team as a Sub System Verification Engineer or Lead Engineer.

The ideal candidate will have a strong background in system design, including experience with verification methodologies and tools. They will be responsible for developing comprehensive test plans, implementing verification flows, and driving functional verification of RTL designs.

  • Develop and implement comprehensive verification test plans for subsystem components and IP's in those sub-system.
  • Build testbenches from scratch for new Sub systems, develop verification flows and test cases using System Verilog and UVM methodology.
  • Drive functional verification of RTL designs at Sub System level or SoC Level including simulation, debugging and coverage closure, ensuring high-quality and robust designs.

The successful candidate will have excellent problem-solving skills, attention to detail, and the ability to work collaboratively in a fast-paced environment. Strong oral and written communication skills are essential, as is the ability to mentor junior verification engineers.

Requirements:

  • Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related fields.
  • Proficiency in verification languages and methodologies, such as SystemVerilog, UVM, and other industry-standard tools.
  • Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and tool integration.
  • Excellent problem-solving skills and attention to detail.
  • Strong oral and written communication skills, with an ability to work as a team player in a fast-paced collaborative environment.
  • 3-15 years of experience in design verification, with a focus on Subsystem/SoC verification.

Responsibilities:

  • Develop and implement comprehensive verification test plans for subsystem components and IP's in those sub-system.
  • Build testbenches from scratch for new Sub systems, develop verification flows and test cases using System Verilog and UVM methodology.
  • Drive functional verification of RTL designs at Sub System level or SoC Level including simulation, debugging and coverage closure, ensuring high-quality and robust designs.

About the Role:

This role offers the opportunity to work on cutting-edge technologies and contribute to the development of complex IP blocks, Subsystems, or SoC Modules. The successful candidate will be part of a highly talented verification team and will have the chance to grow their skills and expertise in a dynamic and collaborative environment.



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