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1 week ago
We are seeking a skilled CPU verification engineer with expertise in SystemVerilog and UVM methodology.
This role involves contributing to the verification of high-performance, low-power CPU cores by developing scalable testbenches and ensuring full functional coverage and quality sign-off.
The ideal candidate will have hands-on experience with RTL simulation and debugging tools and be familiar with scripting languages for automation.
They will also possess a deep understanding of CPU microarchitecture and be able to drive functional and code coverage closure.
Key Responsibilities:- Testbench Development: Develop and maintain UVM-based testbenches for verifying CPU cores and subsystems.
- Test Case Creation: Create directed and random test cases to verify micro architectural features such as pipelines, ALUs, branch prediction, caches, MMUs, etc.
- Functional Coverage: Drive functional and code coverage closure.
- Debugging: Debug failures using waveform tools, logs, and simulation dumps.
- Collaboration: Collaborate with architecture, RTL design, performance, and formal verification teams.
- Verification Planning: Define and implement verification plans, test strategies, and regressions.
- SystemVerilog Expertise: Strong hands-on experience with SystemVerilog and UVM methodology.
- CPU Microarchitecture: Deep understanding of CPU microarchitecture (pipeline, out-of-order execution, caches, TLBs, memory hierarchy).
- RTL Simulation Tools: Expertise in RTL simulation and debugging tools (VCS, ModelSim, Verdi, DVE, etc.).
- Scripting Languages: Familiarity with scripting languages like Python, Perl, or shell for automation.
- Functional Coverage: Good knowledge of functional coverage and assertion-based verification.
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