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Senior Verification Engineer
2 weeks ago
We are seeking a highly skilled and experienced Verification Engineer to join our team.
About the RoleThe ideal candidate will have expertise in UVM and System Verilog, as well as experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage.
Key Responsibilities- Contribute to the development of reusable Verification environments using VMM/OVM/UVM methodologies.
- Develop and maintain Verification Intellectual Property (VIP) for various protocols, including UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, HBM memory protocol.
- Review and sign-off VIP development and updates from a technical perspective, including methodology and protocol functional prospective.
- Liaise with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective.
- Expertise in UVM and System Verilog.
- Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage.
- Familiarity with VMM/OVM/UVM methodologies.
- Protocol experience: UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, HBM memory protocol.
- Opportunity to work on cutting-edge Verification projects.
- Collaborative and dynamic work environment.
- Professional growth and development opportunities.
