
Technical Lead
1 week ago
Job Title: Design Verification Manager
Job Description:
- The candidate will lead critical projects, responsible for end-to-end technical leadership, project execution, and team management within the verification domain.
- Key Responsibilities include defining verification strategies, test plans, coverage goals, and closure metrics in alignment with industry standards.
- Provide technical guidance in SystemVerilog, UVM-based testbench development, coverage closure, debugging, and verification methodologies.
- Collaborate with architects, designers, and engineers across global teams to drive seamless execution.
- Manage multi-site teams, track progress, and mitigate risks through proactive planning.
- Conduct status reporting, milestone reviews, and stakeholder interactions.
- Mentor junior engineers and ensure adherence to best practices in verification and project management.
- Drive continuous improvements in automation, regression efficiency, and verification productivity.
Required Skills & Qualifications:
- 14 to 20+ years of experience in design verification (IP / subsystem / SoC level).
- Strong expertise in SystemVerilog, UVM, SVA, and coverage-driven verification.
- Hands-on knowledge of AMBA protocols (AXI, AHB, APB) and memory/DRAM verification flows.
- Experience with gate-level simulation (GLS), low-power (UPF), and formal verification is a strong plus.
- Exposure to EDA tools such as Cadence Xcelium, Synopsys VCS, and Verdi.
- Proven experience in project/program management, leading DV teams (10+ engineers).
- Strong stakeholder management, planning, and execution skills.
- Excellent communication and leadership skills.
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