
Design Verification Expert
20 hours ago
Leading the way in verification of complex IP blocks or SoC subsystems, our team develops comprehensive test plans and verification strategies based on design specifications.
Key Responsibilities:
- Our verification engineers develop constrained-random and directed testbenches using SystemVerilog/UVM to drive innovation and excellence.
- Collaborating with architects, designers, and other verification engineers, we identify and debug design issues through a collaborative approach.
- Performing functional and code coverage analysis, we strive for perfection and closure.
Required Skills and Qualifications:
- A Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering is essential.
- 8–14 years of hands-on experience in ASIC/SoC verification is required.
- Strong expertise in SystemVerilog, UVM, and RTL simulation tools is necessary.
Preferred Qualifications:
- Experience in formal verification or emulation is a significant advantage.
- Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB) is beneficial.
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