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Senior Semiconductor Layout Designer

3 weeks ago


Bengaluru, Karnataka, India beBeeIoLayout Full time ₹ 9,00,000 - ₹ 12,00,000
IO Layout Specialist

We are seeking a skilled IO Layout Specialist to join our team. As an IO Layout Specialist, you will be responsible for designing and implementing high-quality IO layouts for complex semiconductor devices.

The ideal candidate will have a strong understanding of ESD protection concepts and latch-up avoidance. They will also have expertise in Cadence Virtuoso for layout design and implementation, as well as experience with DRC/LVS tools (Calibre, Assura, PVS). Additionally, they will have familiarity with advanced process technologies (28nm, 16nm, 7nm, FinFET, etc.) and good knowledge of layout-dependent effects (LDE), IR drop, and reliability constraints.

Key Responsibilities:

  • Design and implement full-custom layouts of IO cells, ESD structures, and high-voltage interfaces for ASIC/SoC applications.
  • Work closely with IO circuit designers to interpret schematics and design intent.
  • Ensure robust layout practices for ESD compliance, latch-up prevention, electromigration (EM), voltage isolation, and guard ring planning.
  • Run and close physical verification (DRC, LVS, ERC, ANT) using industry-standard tools.

Required Skills and Qualifications:

  • B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI.
  • 3+ years of hands-on experience in IO and/or ESD layout.
  • Strong understanding of ESD protection concepts and latch-up avoidance.
  • Expertise in Cadence Virtuoso for layout design and implementation.
  • Experience with DRC/LVS tools (Calibre, Assura, PVS).
  • Familiarity with advanced process technologies (28nm, 16nm, 7nm, FinFET, etc.).

Preferred Qualifications:

  • Experience in high-voltage or multi-voltage IO layout (1.8V/3.3V/5V interfaces).
  • Experience with IO ring planning and integration in complex SoC floorplans.

Job Summary: We are looking for a highly motivated and experienced IO Layout Specialist to join our team. The candidate will be responsible for designing and implementing high-quality IO layouts for complex semiconductor devices.