
Senior RTL Principal Designer
21 hours ago
This is an exceptional opportunity to work as a Senior RTL Principal Design Engineer.
The ideal candidate should have 8-16 years of experience in core RTL design using Verilog, with a strong background in System Verilog and UVM based environment usage/debugging.
Experience in implementing complex protocols and prior experience in IP development teams is highly desirable.
Main Responsibilities:- Design and support of the RTL for PCIe/CXL/IDE/UALink IP solution.
- Work with existing RTL to add new features and ensure various customer configurations are clean as part of verification regressions.
- Support customers by ensuring design cleanliness for LINT and CDC design guidelines.
Skill in scripting is beneficial for this role.
Key Performance Indicators (KPIs):
- Design quality and performance.
- Timely completion of projects.
- Cross-functional collaboration.
What We Offer:
- A dynamic working environment.
- Ongoing professional development opportunities.
- A competitive remuneration package.
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