
RTL Architect
2 days ago
Job Opportunity
">Tessolve Semiconductor is seeking experienced RTL Design Engineers and Design Verification Engineers for our Bangalore location.
We require:
- 5+ years of experience in ASIC/IP design
- Proficiency in RTL ASIC, CDC, Lint, Synthesis, and Spyglass
- Experience with Logic design / RTL design
- Knowledge of IP design and integration
- Expertise in using tools like Lint and CDC for ASIC development
- Understanding of timing concepts and Synthesis
- Familiarity with AMBA protocols (AXI, AHB, APB) and SoC clocking/reset architecture
The ideal candidate will also have experience in:
- IP verification using SV/UVM
- SOC verification using C/SV
- Third-party VIP integration
- Interconnect protocols (AHB, AXI, APB)
- SOC interfaces (GPIO, SPI, I2C, UART)
- High-speed serial interfaces (PCIe Gen 3/4 or USB or MIPI)
- Memory interfaces (DDR or HBM I/O)
- Coverage closure (Code, Functional, and Toggle)
- Technical documentation (Testbench Specification, Test Plan Specification)
- Foundry porting experience (Technology Library Conversion Related Changes Verification)
Interested candidates should submit their updated CV and connect on LinkedIn.
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