Senior Digital Fault Tolerance Expert

1 week ago

Dombivli, Maharashtra, India beBeeDFT Full time ₹ 1,50,00,000 - ₹ 2,19,00,000
Job Title: Lead DFT Engineer

We are seeking a seasoned engineer with expertise in Digital Fault Tolerance (DFT) to drive the architecture, planning, and implementation of complex System-on-Chip (SoC)/Application-Specific Integrated Circuit (ASIC) designs.

The ideal candidate will have 7+ years of experience in DFT for advanced node designs (e.g., FinFET) and be proficient in leading teams and mentoring junior engineers.

Key Responsibilities:
  • Develop and implement DFT strategies and architectures for multiple projects.
  • Implement and verify various DFT features like scan insertion and compression, ATPG pattern generation, Memory BIST, boundary scan, and IJTAG.
  • Manage the end-to-end DFT flow from Register-Transfer Level (RTL) to silicon bring-up.
  • Collaborate with cross-functional teams for seamless integration.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Ensure DFT signoff, timing closure, and ATE pattern delivery.
Required Skills and Experience:
  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.
  • Strong knowledge of RTL design, Static Timing Analysis (STA), and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
Preferred Qualifications:
  • Experience with hierarchical DFT and low-power DFT methodologies.
  • Familiarity with safety-critical designs and functional safety.
  • Experience working in advanced nodes (e.g., 7nm, 5nm).

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