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Analog Mixed Signal Verification Expert
2 weeks ago
Key Responsibilities:
">- Drive verification of complex AMS IPs and subsystems (PLLs, ADCs/DACs, SerDes, LDOs, power management circuits) at both IP and SoC integration levels.
- Develop Verilog-AMS and SystemVerilog RNM models for analog IPs to enable faster top-level verification.
- Build and enhance UVM-MS based mixed-signal verification environments.
- Perform co-simulation of analog (SPICE) and digital (SystemVerilog) domains using industry tools.
- Define and implement assertion-based and coverage-driven verification methodologies for AMS designs.
- Collaborate with circuit designers on corner case and Monte Carlo verification.
- Automate verification workflows using Python, Perl, or TCL scripting.
Requirements:
- 5+ years of AMS verification experience in IP or SoC environments.
- Hands-on expertise with Verilog-AMS, SystemVerilog, UVM-MS methodologies.
- Strong knowledge of SPICE-level simulation (Spectre, HSPICE, Eldo, FineSim).
- Experience with AMS co-simulation flows (Cadence AMS Designer, Synopsys VCS AMS, Questa ADMS).
- Proven experience in developing behavioral/real-number models (RNM) for analog blocks.
- Good understanding of analog circuit behavior (PLLs, ADC/DAC, SerDes, regulators, power circuits).
Preferred Skills:
- Exposure to advanced nodes (7nm, 5nm, FinFET).
- Familiarity with formal verification techniques for AMS.
- Hands-on with mixed-signal emulation/prototyping.
- Prior involvement in tapeout and silicon validation.
Education:
Bachelor's or Master's degree in Electronics, Electrical, or VLSI Engineering is preferred but not required. Relevant work experience can be considered in lieu of formal education.