Senior Verification Expert for Complex IPs
4 days ago
Baya Systems is seeking a seasoned Design Verification Engineer to join our team in Bangalore, India.
We offer a highly competitive salary of ₹2,200,000 - ₹3,300,000 per annum, depending on experience.
About the RoleThe ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions.
In this role, you will collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems.
- You will write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards.
- Collaborate with software teams to define and implement configurable testbenches.
- Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.
To succeed in this position, you will need:
- A BS/MS in Electrical Engineering, Computer Engineering or Computer Science.
- 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification.
- Proficiency in Verilog, SystemVerilog.
- Familiarity with industry-standard EDA tools for simulation and debug.
- Deep experience with UVM-based testbenches.
- Experience with modern programming languages like Python.
- Knowledge of ARM AMBA protocols such as AXI, APB, and AHB.
- Understanding of ARM CHI protocol is a plus.
- Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs.
- Experience with formal verification techniques, emulation platforms is a plus.
- Excellent problem-solving skills and attention to detail.
- Strong communication and collaboration skills.
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