Senior Design Validation Expert

23 hours ago

Jamnagar, Gujarat, India beBeeVerification Full time ₹ 60,00,000 - ₹ 1,00,00,000
Principal Design Verification Engineer

We are seeking a skilled Principal Design Verification Engineer to lead the verification of complex IP blocks or SoC subsystems. The ideal candidate will have a strong background in pre-silicon verification and be capable of leading verification efforts across multiple projects.

The successful candidate will develop test plans, verification strategies, and coverage metrics based on design specifications. They will also build and maintain constrained-random and directed testbenches using SystemVerilog/UVM.

In addition to these responsibilities, the candidate will collaborate with architects, designers, and other verification engineers to identify and debug design issues. They will also provide technical guidance and mentorship to junior team members.

Requirements:

  • Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering.
  • 8–14 years of hands-on experience in ASIC/SoC verification.
  • Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa).
  • Solid understanding of verification methodologies, functional coverage, and assertion-based verification.
  • Experience in developing and maintaining testbenches from scratch.
  • Strong debugging skills and familiarity with waveform viewers like Verdi or DVE.
  • Good knowledge of scripting languages (Python, Perl, or TCL) for automation.
  • Familiarity with version control and CI/CD systems.

Preferred Qualifications:

  • Experience in formal verification or emulation.
  • Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB).
  • Prior experience in leading a verification team or acting as a verification lead.
  • Exposure to post-silicon bring-up and validation.

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