
Formal Verification Expertise Seeker
5 days ago
As a Formal Verification Engineer, you will play a crucial role in developing and executing formal verification strategies for IP and SoC blocks. Your primary responsibility will be to design and implement effective verification plans that ensure the correctness of complex designs.
Key Responsibilities:- Develop and execute formal verification strategies for IP and SoC blocks
- Write and prove assertions using SystemVerilog Assertions (SVA) or PSL
- Use tools like JasperGold, VC Formal, or OneSpin to verify complex designs
- Collaborate with design and DV teams to integrate formal early in the cycle
- Identify corner-case bugs that are hard to detect via simulation
To succeed in this role, you will need the following skills and qualifications:
- 4-12 years of experience in formal verification
- Strong knowledge of SystemVerilog Assertions (SVA) or PSL
- Experience with tools like JasperGold, VC Formal, or OneSpin
- Excellent collaboration and communication skills
- Ability to work effectively in a team environment
We offer a competitive salary and benefits package, including:
- Opportunity to work on challenging projects and develop your skills
- Collaborative and dynamic work environment
- Professional growth and development opportunities
- Recognition and rewards for outstanding performance
ACL Digital is a leader in digital engineering and transformation. We empower organizations to thrive in an AI-first world by seamlessly integrating AI and data-driven solutions from chip to cloud. Our expertise spans the entire technology stack, and we are committed to helping our clients navigate the complexities of digital transformation.
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