
Senior Static Timing Analysis Specialist
1 week ago
A challenging opportunity exists for a seasoned Static Timing Analysis (STA) specialist to lead STA and Place and Route (PNR) activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
- Lead STA and PNR activities for large, multi-block or hierarchical subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).
- Develop and refine methodologies for STA and PNR tailored to the unique challenges of complex subsystem integration.
- Drive automation and validation of timing and physical design data across subsystem boundaries.
- 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design.
- Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus).
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
- Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
- Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams.
This is an excellent opportunity to work with a talented team of engineers, drive innovation, and take your career to the next level. If you have a passion for STA and PNR, we encourage you to apply.
Other Requirements:- Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level is preferred.
- Background in high-speed interfaces, or mixed-signal SoC subsystems is beneficial.
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