Senior Verification Specialist

2 days ago

Thiruvananthapuram, Kerala, India beBeeVerification Full time ₹ 15,00,000 - ₹ 20,00,000

Job Title: Senior Design Verification Engineer

Job Description:

We are seeking an experienced verification engineer to join our team.

The successful candidate will have a strong background in digital design and be proficient in the use of formal verification tools.

  • Understanding business requirements and functional specifications of IPs, subsystems, and SOC is crucial for this role.
  • Developing a verification environment architecture document is a key responsibility.
  • Reviewing and revising work towards meeting agreed-upon acceptance criteria is essential.
  • Proficiency in System Verilog, UVM (Universal Verification Methodology), C programming languages for unit, subsystem, and SOC-level verification is required.
  • Performing RTL simulations using Synopsys and Cadence simulators is a critical skill.
  • Debugging and resolving problems found by simulations is an important aspect of this role.
  • Development of performance test plans and maintenance is a key responsibility.
  • Creation of transactors, monitors, and models for performance verification is required.
  • Implementation of performance verification flow including monitoring, synchronization, reporting, and self-checking mechanisms is crucial.
  • Providing full reports of performance metrics and bottlenecks is essential.
  • Tracking tickets and code releases using Bug Tracking tool and GIT is a key responsibility.
  • Performance of UPF (Unified Power Format) based power-aware simulations is required.
  • Coding assertion and functional coverage bins in SVA (System Verilog Assertions) is a critical skill.
  • Code and functional coverage closure is essential.
  • Preparation and conducting reviews of verification sign-off documents to ensure SOC tape-out quality is a key responsibility.

Required Skills and Qualifications:

7+ years of experience in digital design verification.

Strong background in System Verilog, UVM (Universal Verification Methodology), C programming languages.

Experience with RTL simulations using Synopsys and Cadence simulators.

Proficiency in development of performance test plans and maintenance.

Knowledge of creation of transactors, monitors, and models for performance verification.

Ability to implement performance verification flow including monitoring, synchronization, reporting, and self-checking mechanisms.

Excellent debugging and problem-solving skills.

Good communication and teamwork skills.

Benefits:

Opportunity to work on cutting-edge projects.

Collaborative and dynamic work environment.

Competitive salary and benefits package.

Others:

Must be able to work in a fast-paced environment.

Must be able to adapt to changing priorities.

Must be able to maintain confidentiality.

Background check may be required.

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