Senior Design Verification Expert

9 hours ago

Thrissur, Kerala, India beBeeVerification Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

We are seeking an experienced and passionate Design Verification Specialist to contribute to the development of complex IPs or SoCs.

The ideal candidate will have a strong background in pre-silicon verification and be capable of leading verification efforts across multiple projects.

  • Lead and contribute to the verification of complex IP blocks or SoC subsystems.
  • Develop test plans, verification strategies, and coverage metrics based on design specifications.
  • Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM.
  • Collaborate with architects, designers, and other verification engineers to identify and debug design issues.
  • Develop and maintain verification infrastructure, scripts, and regression systems.
  • Perform functional and code coverage analysis, driving closure.
  • Provide technical guidance and mentorship to junior team members.
  • Participate in silicon bring-up and post-silicon validation when needed.
Required Skills and Qualifications:
  • Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering.
  • 8–14 years of hands-on experience in ASIC/SoC verification.
  • Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa).
  • Solid understanding of verification methodologies, functional coverage, and assertion-based verification.
  • Experience in developing and maintaining testbenches from scratch.
  • Strong debugging skills and familiarity with waveform viewers like Verdi or DVE.
  • Good knowledge of scripting languages (Python, Perl, or TCL) for automation.
  • Familiarity with version control and CI/CD systems.
Preferred Qualifications:
  • Experience in formal verification or emulation is beneficial.
  • Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB).
  • Prior experience in leading a verification team or acting as a verification lead.
  • Exposure to post-silicon bring-up and validation.

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