Senior ASIC Test Specialist

2 days ago

Allahabad, Uttar Pradesh, India beBeeEngineering Full time ₹ 15,00,000 - ₹ 20,00,000
Job Role: ASIC Test Engineer

The ideal candidate will be responsible for creating and implementing test strategies for application-specific integrated circuits (ASICs).

  • Developing and executing comprehensive test plans to ensure thorough coverage of all device aspects.
  • Implementing automatic test pattern generation (ATPG) techniques to minimize testing time.
  • Collaborating with cross-functional teams to develop and implement new test methodologies.
  • Analyzing and debugging issues that arise during testing.

Main Responsibilities:

  • ADC/DAC Testing - Analogue-to-digital converters and digital-to-analogue converters.
  • Internal loopback, SCAN (stuck-at and transition delay), Pre & Post-trim including temperature sensors, IO DC parametric tests, Process monitor / ring oscillator tests.
  • SERDES (CPRI, PCIE) Testing - Internal & external loopback – external loopback at package only, IO DC parametrics tests, Register/PLL lock checks using either APB or iJTAG for access, Stuck-at and Transition Delay SCAN, IDD (Current into VDD supply pin) – if separate power supply available.
  • ATPG (Automatic Test Pattern Generation)
  • Boundary Scan (BSDL, Boundary Scan Description Language)) - IEEE1149.1 & IEEE1149.6.
  • Programming LTU chip
  • Process Monitors (ProteanTec / Synopsys)
  • High Voltage Stress Testing – Cyclic Alternating Voltage Stress per TSMC.
  • Very Low Voltage (VLV) Testing
  • IO Parametric Tests – leakage, Vix, Vox.
  • IDD – quiescent/gross, functional/dynamic, sleep.
  • Top Level Verification (TLV) functional patterns, e.g., Path Delay, if any.
  • Processor Performance (Coremark/Dhrystone) patterns.
  • Temperature Sensor(s) – SoC - calibration & reading.
  • Characterization & Correlation – perform characterization across PVT, correlate against golden data.
  • Production Test & Yield Ramp – optimize test time, support binning, yield analysis.
  • Failure Analysis Support – debug routines (shmoo, scan diagnosis), provide reports.

Required Skills:

  • Minimum 5+ years experience in ASIC Test Engineering.
  • Strong knowledge of digital circuit design and testing principles.
  • Excellent problem-solving and analytical skills.
  • Ability to work independently and as part of a team.
  • Proficiency in programming languages such as Python, C++, and Java.

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