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ASIC SOC RTL Design Lead
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Vizag, Andhra Pradesh, India Eximietas Design Full timeHi All, Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. We are Hiring: Senior ASIC SOC RTL Design Leads Location: Visakhapatnam or Bangalore Experience: 10+ Years. ❖ Minimum Qualifications: Bachelor's degree in Computer Science,...
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Vizag, Andhra Pradesh, India Eximietas Design Full timeHi All,Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains.We are Hiring: Senior ASIC SOC RTL Design LeadsLocation: Visakhapatnam or BangaloreExperience: 10+ Years.❖ Minimum Qualifications: Bachelor's degree in Computer Science,...
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ASIC SOC RTL Design Lead
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Vizag, Andhra Pradesh, India Eximietas Design Full timeHi All, Greetings' from Eximietas Design.... We are Hiring ASIC SOC RTL Design Engineer/Leads. Job Title: ASIC SOC RTL Design Engineer/Leads .. Experience: 8+ Years. Location: Visakhapatnam. Job Description: Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play...
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ASIC SOC RTL Design Lead
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Vizag, Andhra Pradesh, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..Experience: 8+ Years.Location: Visakhapatnam.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play a critical role...
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Vizag, Andhra Pradesh, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..Experience: 10+ Years.Location: Vizag or Bangalore.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play a...
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ASIC SOC RTL Design Lead
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Vizag, Andhra Pradesh, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..Experience: 8+ Years.Location: Visakhapatnam or Bangalore.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play a...
Senior ASIC Designer
2 weeks ago
We are seeking a seasoned Physical Design Engineer to join our team. This is an exciting opportunity to work on cutting-edge projects and collaborate with experienced professionals.
- The successful candidate will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.
- Experience with EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc. is highly desirable.
- The ideal candidate will work closely with the methodology team to solve implementation challenges and provide inputs to improve the Physical design flow.
- Strong experience in design automation, understanding of Timing constraints, SI prevention, Power reduction, and proficiency in Unix/TCL/Perl are essential.
- Prior experience with Synopsys/Cadence/Mentor place and route tools, particularly in 16nm and/or 7nm process nodes, is required.
To be considered for this position, you should have:
- At least 4+ years of experience in ASIC physical design.
- Strong communication skills and ability to work effectively in a team environment.
- Hands-on experience with TCL/Perl development.
The following qualifications are highly desirable:
- Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project.
- Track record of taping out complex chips on advanced process nodes.
