Design Verification Manager
21 hours ago
We are seeking a hands-on, experienced and dynamic Design Verification Manager with a deep understanding of digital design principles, interface protocols, memory protocols, and SoC verification methods. The ideal candidate will lead our verification team to ensure the quality and reliability of our digital designs, utilizing advanced verification methodologies such as SystemVerilog and UVM.
About Us
Mulya Technologies is a technology consulting company delivering best-in-class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills. Our embedded design services are centered around FW validation & Test Automation. We support a mix of engagement models to support diverse client requirements.,
"$150,000 - $180,000 per year" based on experience and qualifications, Mulya Technologies offers an attractive salary for this position. Experience in leading cross-functional teams has earned us recognition as one of the industry leaders.
Key Responsibilities:
- Team Leadership
- Lead, mentor, and manage a team of verification engineers.
- Foster a collaborative and innovative team environment.
- Develop team skills through training and professional development initiatives.
- Verification Strategy
- Define and implement verification plans for digital designs, including SoCs.
- Develop and maintain verification environments using SystemVerilog and UVM.
- Ensure comprehensive verification coverage for all design blocks and system-level integration.
- Project Management
- Plan and estimate verification tasks, resources, and schedules.
- Track and report on verification progress, ensuring timely delivery of verification milestones.
- Coordinate with cross-functional teams, including design, architecture, and software, to align verification activities with project goals.
- Technical Expertise
- Lead the development and execution of test plans, testbenches, and test cases.
- Perform and oversee gate-level simulations, including timing analysis and power estimation.
- Apply knowledge of interface protocols (e.g., PCIe, Ethernet), memory protocols (e.g., DDR, HBM), and SoC verification methods to ensure design quality.
- Identify and resolve complex design and verification issues.
- Education
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience
- 12+ years of experience in digital design verification.
- Skills
- Deep understanding of digital design principles and verification methodologies.
- Proficiency in SystemVerilog and UVM for verification.
- Experience with gate-level simulation and timing analysis.
- Strong knowledge of interface protocols (e.g., PCIe, Ethernet) and memory protocols (e.g., DDR, HBM).
- Familiarity with SoC verification methods and tools.
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