Senior DFT Architect Position

3 days ago

Kottayam, Kerala, India beBeeDft Full time ₹ 20,00,000 - ₹ 25,00,000
Job Title: DFT Architect

We are seeking a seasoned Digital Forensic Techniques (DFT) architect to lead the design and implementation of DFT architecture for complex System-on-Chip (SoC)/Application-Specific Integrated Circuit (ASIC) designs. The successful candidate will be responsible for defining and driving DFT strategy, planning, and execution across multiple projects. They will also mentor junior engineers and collaborate with cross-functional teams to ensure world-class testability and manufacturability of silicon products.

Main Responsibilities:
  1. DFT Strategy and Architecture: Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
  2. Implementation and Verification: Lead implementation and verification of DFT features such as scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), and IJTAG (1687).
  3. End-to-End DFT Flow Management: Manage end-to-end DFT flow – from RTL to gate-level netlist and silicon bring-up.
  4. Collaboration and Communication: Collaborate with RTL, STA, PD, and test engineering teams for seamless integration, perform pattern generation, fault simulation, and debug test coverage gaps.
  5. Signoff and Timing Closure: Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
  6. Silicon Bring-Up and Test Vector Validation: Support silicon bring-up, test vector validation on ATE, and yield optimization.
  7. Mentorship and Training: Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
  8. DFT Automation: Develop and maintain DFT automation scripts and infrastructure.

Required Skills and Qualifications:

  1. Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  2. At least 7 years of experience in DFT for complex ASIC or SoC designs.
  3. Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  4. Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.
  5. Strong knowledge of RTL design, STA, and synthesis flows.
  6. Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
  7. Deep understanding of silicon test challenges and test coverage improvement.
  8. Strong leadership, team collaboration, and communication skills.

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