Principal ASIC Verification Engineer
3 weeks ago
Key Responsibilities:
Develop testbenches using System Verilog and UVM for functional and power-aware RTL verification.
Design and implement UVM components, including agents, scoreboards, and environments, to enhance verification efficiency.
Create assertions and functional coverage to ensure comprehensive verification of the design.
Collaborate with the team to identify and close gaps in functional, power-aware, and gate-level timing simulation.
Develop C test cases for HW-FW simulation and FPGA prototyping.
Set up and debug RTL and gate-level netlists using regression testing.
Review industry-standard specifications and update the test plan to improve verification quality.
Participate in post-silicon bring-up, validation, and compliance testing, and debug.
Work closely with cross-functional teams, including ASIC Architects, Designers, and Firmware Development teams, to ensure successful product delivery.
Qualifications:
Proven track record of verification, taking several chips from specification to tape out.
Expertise in UVM and/or System Verilog-based verification.
Strong understanding of ASIC verification methodologies and experience in achieving verification closure.
Experience working with source control tools, bug management tools, and release management tools like Jenkins, Git, and Jira.
Familiarity with SoC interfaces, embedded processors, networking protocols, security protocols, and video formats is a significant advantage.
Exceptional written and verbal communication skills, with the ability to work independently.
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