Senior Digital Systems Engineer
2 weeks ago
InnoPhase Inc., DBA GreenWave Radios, a pioneer in Open RAN digital radios, is revolutionizing the industry with cutting-edge solutions. Our Hermes64 RF SoC-powered designs enhance network energy efficiency and reduce operational expenses.
Headquartered in San Diego, California, GreenWave Radios has established a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a talented team of over 100 engineers worldwide and an extensive portfolio of over 120 global patent filings.
GreenWave Radios and Synergic Emergence have a co-employment relationship, providing employees with access to premium benefits and services through Synergic Emergence's professional employment organization.
About the Job:
As a Technical Lead - VLSI Design, you will be instrumental in ORAN SoC product development, collaborating with firmware and design teams to define product requirements and micro-architecture. You will participate in implementing and verifying novel ORAN SoC functional blocks for high-performance applications like LTE and sub-6 GHz 5G cellular base stations.
You will interface with project coordinators to track schedules and dependencies, provide technical guidance to junior engineers, and contribute to ensuring the quality of work.
This role offers an exceptional opportunity for experienced engineers with 10+ years of industrial experience to grow their technical career and leadership skills while contributing to the exciting cellular product market space.
Key Responsibilities- Participate in SoC specifications reviews and contribute to micro-architecture definitions.
- Front-end digital design and implementation - RTL Coding, Lint, CDC, and Synthesis.
- Develop design constraints and coordinate to debug both functional and DFT test issues.
- Supervise/mentor young engineers for task assignment and ensure productivity and quality.
- Project coordination and status update.
- Debug designs, provide timely closure, and help improve SoC design methodologies and verification quality.
- Support IP/design verification/fw/sw/system/production teams to provide necessary support for timely closure of assigned blocks design and implementation issues.
- Masters and/or Bachelors degree in engineering (or equivalent) in EC/EE/CS with 10 or more years of experience in digital SoC development.
- Experience in RTL design using Verilog/VHDL and SystemVerilog for CPU/control sub-systems (AXI/AHB/APB bus, PCIe, PIPE interface), digital signal processing blocks (FIR filter, FFT/IFFT, NCO) & Analog Serdes block.
- Experience of front-end tools (Verilog simulators, linters, clock-domain-crossing checkers).
- Experience in Gate Level Simulation (GLS) and LEC checking.
- Good understanding on back-end design flow on logic synthesis, constraints, timing analysis, DFT etc.
- Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques.
- Knowledge of languages such as C/C++, Perl, Tcl, and Python.
- Good verbal and written communication and presentation skills.
- Team player with ability to collaborate with cross-functional teams to resolve issues effectively.
- Competitive salary and stock options.
- Learning and development opportunities.
- Employer-paid health insurance.
- Earned, casual, sick, and parental leaves.
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