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Analog Layout Design Expert

2 weeks ago

Bengaluru, Karnataka, India Cadence Design Systems Full time
Cadence SerDes IP Team Overview

The Cadence Design Systems SerDes IP team is dedicated to creating cutting-edge FinFET technologies. As a key member of our team, you will play a crucial role in developing High Speed Analog and Mixed-Signal SerDes IP for Tier-1 customers.

We are seeking an experienced Lead Design Engineer who can lead the design and development of analog IP like Opamps, Bandgaps, Dataconverters, LDO and PLL etc.

You will be responsible for understanding layout effects on the circuit such as speed, capacitance, power and area etc., and applying various analog layout techniques like matching, shielding etc.,

A good understanding of DSM technology methodology, issues etc., and experience working on latest technology nodes, 28nm and below, is highly desired.

Please find below the key responsibilities and qualifications for this position:

Key Responsibilities:
  • Design and development of analog IP like Opamps, Bandgaps, Dataconverters, LDO and PLL etc.
  • Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
  • Applying various analog layout techniques like matching, shielding etc.

Qualifications:
  • Bachelor's or Master's degree in Electronics Engineering or related field.
  • Minimum 5 years of experience in analog design and layout.
  • Strong knowledge of analog layout tools and methodologies.

Benefits:
  • Competitive salary and benefits package.
  • Opportunities for professional growth and development.
  • Collaborative and dynamic work environment.

How to Apply:

Please submit your resume and cover letter to us via email.