
Senior Network Architect
4 days ago
Job Title: Principal IP/RTL Design Engineer for Ethernet Switch
Job Summary:
We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks.
- Main Responsibilities:
- Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches.
- Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals.
- Optimize designs for low latency, high throughput, and power efficiency.
- Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control.
- Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation.
- Use P4 or related languages for programmable packet processing.
- Collaborate with teams for synthesis, timing closure, and IP integration.
- Document designs and stay updated on AI networking trends.
Requirements:
To be successful in this role, you will need:
- Education: BS/MS/PhD in Electrical or Computer Engineering.
- Technical Skills:
- Proficient in Verilog/SystemVerilog for design.
- Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control.
- Experience with InfiniBand, NVLink, or similar protocols.
- Proficiency in P4 or programmable data plane languages.
- Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE.
- Familiarity with power optimization or SDN.
- Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools.
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