Verification Environment Architect

2 days ago


Dombivli, Maharashtra, India beBeeVerification Full time ₹ 2,20,00,000 - ₹ 2,62,50,000

Job Overview:

This role leads the development of a verification environment from scratch. The successful candidate will oversee architecture collaboration with design and architecture teams, creating test plans and implementing top-down DV flows for robust and re-usable DV environments across various devices.

Main Responsibilities:

  • DV methodology architecting, flow development, test plan creation, and execution
  • Chip verification in cooperation with design, architecture, system validation, and software teams
  • DV testing plans: proposing appropriate DV strategies, building test platforms, developing test cases, and ensuring verification quality with coverage tools

Essential Qualifications:

  • In-depth DV experience of at least 10 years in building test environments from scratch is required, involving understanding specifications, comprehensive test plan creation, architecting top-level testbenches, and associated environments, leading to coverage closure.
  • Expertise with verification tools (e.g. Verilog, SystemVerilog, UVM, OVM)
  • Experience in standards-based verification like MIPI, USB3, Ethernet is preferred.
  • Experience in DV of power-aware designs is preferred.
  • A self-motivated individual capable of devising verification strategies for new devices without legacy references.
  • Possesses hands-on skills and motivation to contribute individually towards exciting product developments.

About the Opportunity:

This is an exciting opportunity to build industry-first products with a motivated team. The ideal candidate should be a self-starter who can come up with innovative solutions and collaborate effectively with cross-functional teams.



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