Design for Testability Specialist

Job SummaryWe are seeking a highly skilled Design for Testability Specialist to join our team at MaimsD Technology. As a key member of our engineering team, you will be responsible for designing and implementing testability solutions for our digital circuits.Key Responsibilities- Develop and implement DFT methodologies, including scan, ATPG, MBIST, JTAG,...

We are seeking a skilled Design for Test (DFT) Engineer to join our dynamic team. The DFT Engineer will play a crucial role in ensuring the testability and manufacturability of our integrated circuits (ICs). The successful candidate will collaborate closely with the design, verification, and test teams to develop and implement DFT techniques that optimize...

We are seeking a skilled Design for Test (DFT) Engineer to join our dynamic team. The DFT Engineer will play a crucial role in ensuring the testability and manufacturability of our integrated circuits (ICs). The successful candidate will collaborate closely with the design, verification, and test teams to develop and implement DFT techniques that...

We are seeking a skilled Design for Test (DFT) Engineer to join our dynamic team. The DFT Engineer will play a crucial role in ensuring the testability and manufacturability of our integrated circuits (ICs). The successful candidate will collaborate closely with the design, verification, and test teams to develop and implement DFT techniques that optimize...

Job DescriptionWe are seeking a highly skilled Design for Testability Engineer to join our team at SARVAJITH INFOTECH.Key Responsibilities:Design and implement testability features in electronic designsDevelop and maintain test plans and proceduresCollaborate with cross-functional teams to ensure testability requirements are metConduct fault detection and...

Role : DFTLocation : BangaloreExperience: 3 - 15 YrsEmployment Type : Full Time, PermanentWorking mode : RegularNotice Period : Immediate - 15 DaysKey Responsibilities :DFT Methodology Expertise :- Deep understanding of DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG.- Proficiency in industry-standard EDA tools for DFT implementation...

Role : DFTLocation : BangaloreExperience: 3 - 15 YrsEmployment Type : Full Time, PermanentWorking mode : RegularNotice Period : Immediate - 15 DaysKey Responsibilities :DFT Methodology Expertise :- Deep understanding of DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG.- Proficiency in industry-standard EDA tools for DFT implementation...

Now we are looking for Design for testability role.Interview Process - One or two round of internal interviews and then HR Max Budget for each role - 4XNumber of working days - 5 DaysMandatory areas/skills for all the 5 roles - NP : Immediate or 30daysMandatory skills :- DFT- JTAG- ATPG- MBIST- SCAN DFT : 15 - 20 YearsJD :- Hands on experience in various...

Now we are looking for Design for testability role.Interview Process - One or two round of internal interviews and then HR Max Budget for each role - 4XNumber of working days - 5 DaysMandatory areas/skills for all the 5 roles - NP : Immediate or 30daysMandatory skills :- DFT- JTAG- ATPG- MBIST- SCANDFT : 15 - 20 YearsJD :- Hands on experience in various DFT...

Mirafra Technologies Hiring Position : DFT Director – Design for Testability (DFT) Location : Bangalore Experience Level : 14+ years in semiconductor design, with extensive expertise in DFT methodologies About the Role We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a...

Mirafra Technologies Hiring Position : DFT Director – Design for Testability (DFT) Location : Bangalore Experience Level : 14+ years in semiconductor design, with extensive expertise in DFT methodologies About the Role We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a...

Mirafra Technologies Hiring Position : DFT Director – Design for Testability (DFT) Location : Bangalore Experience Level : 14+ years in semiconductor design, with extensive expertise in DFT methodologies About the Role We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in...

Mirafra Technologies HiringPosition: DFT Director – Design for Testability (DFT)Location: BangaloreExperience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologiesAbout the RoleWe are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining,...

Mirafra Technologies Hiring Position : DFT Director – Design for Testability (DFT) Location : Bangalore Experience Level : 14+ years in semiconductor design, with extensive expertise in DFT methodologies About the Role We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in...

Mirafra Technologies HiringPosition: DFT Director – Design for Testability (DFT)Location: BangaloreExperience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologiesAbout the RoleWe are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining,...

Roles And Responsibilities - 10 years+ Experience in complex SOC level DFT execution in advanced finFET technology. - Strong DFT fundamental knowledge from defect models to ATPG algorithm. - Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent. - Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with...

Roles And Responsibilities 10 years+ Experience in complex SOC level DFT execution in advanced finFET technology. Strong DFT fundamental knowledge from defect models to ATPG algorithm. Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent. Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic...

Roles And Responsibilities 10 years+ Experience in complex SOC level DFT execution in advanced fin FET technology. Strong DFT fundamental knowledge from defect models to ATPG algorithm. Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent. Knowledge of basic So C architecture and HDL languages like Verilog to be able to work with logic...

Roles And Responsibilities- 10 years+ Experience in complex SOC level DFT execution in advanced finFET technology.- Strong DFT fundamental knowledge from defect models to ATPG algorithm.- Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.- Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic...

Roles And Responsibilities10 years+ Experience in complex SOC level DFT execution in advanced finFET technology.Strong DFT fundamental knowledge from defect models to ATPG algorithm.Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design...