
Lead Designer for Advanced Digital Systems
5 days ago
Design and Develop High-Quality Digital IP Blocks
- Create high-quality Register-Transfer-Level (RTL) designs using Verilog or SystemVerilog.
- Develop and maintain complex digital IP blocks with a strong focus on design verification, synthesis, and timing closure.
- Collaborate with cross-functional teams to integrate designs into System-on-Chip (SoC) architectures, adhering to AXI bus protocols and hardware debugging best practices.
- Work with Xilinx FPGAs and Vivado tool flows, with experience in microarchitecture development highly valued.
Requirements:
- A minimum of 3-5 years of experience in RTL design engineering.
- Strong foundation in logic synthesis and timing closure concepts.
- Good knowledge of SoC architecture, AXI bus protocols, and hardware debug.
- Ability to write simple testbenches for design verification.
Benefits of the Role:
This position offers an exciting opportunity to work on cutting-edge projects and develop your skills in digital IP block design and development. You will be part of a dynamic team that values collaboration and innovation.
About the Ideal Candidate:
We are looking for a talented engineer who is passionate about digital design and development. If you have a strong foundation in RTL design engineering and a keen interest in developing complex digital IP blocks, we would love to hear from you.
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