Senior Verification Engineer

2 weeks ago

Bengaluru, Karnataka, India beBeeVerification Full time ₹ 15,00,000 - ₹ 28,00,000
Job Description

The role involves leading the verification of complex proprietary DSP IP with an emphasis on power-aware verification. This entails designing and implementing SystemVerilog testbench environments following UVM/OVM methodologies, developing comprehensive verification plans, and executing simulation, assertions, formal verification, and HW-SW co-verification.

Additionally, the candidate will drive power-aware RTL simulation using UPF methodologies, perform detailed debugging and simulation tasks to ensure product quality, and automate verification processes with scripting and verification tools to improve efficiency and quality.

The successful candidate will ensure coverage goals and deliver high-quality commercial-ready IP.
Required Skills & Qualifications

  • A strong background in digital design, processor architecture, and power-aware verification is required.
  • Expertise in SystemVerilog testbench architecture and implementation (OVM/UVM) is essential.
  • Proficiency in UPF and power-aware RTL simulations is also necessary.
  • Experience with simulators/tools from Synopsys, Mentor, or Cadence is desirable.
  • Familiarity with hardware verification languages (SystemVerilog, VERA), and hardware description languages (Verilog, SystemVerilog) is a must.
  • Knowledge of AMBA protocols (AHB, AXI, APB) and debug protocols is also required.
  • Good understanding of Object-Oriented Programming (OOP) concepts is necessary.
  • Scripting and automation skills: Perl, Python, Shell scripting, Makefile, TCI are highly desirable.

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