
Senior FPGA Design Flow and Validation Expert
9 hours ago
The post of Principal Engineer - FPGA Design Flow & Validation involves contributing to the development of cutting-edge FPGA design flow and validation projects.
Key responsibilities include:
- Design Flow Optimization
- RTL Implementation, Protocols (PCIe, Ethernet, DDR4/5, Memory)
- Integration-focused role: 80% Integration, 20% Design
- System-level Testing & Validation
- Debugging Interfaces and Design-level Debugging
- Board-level Debugging (20:80 simple design & debug split)
Requirements for the position include:
- Expertise in RTL design and implementation
- Strong knowledge in FPGA design flow and validation
- Experience with system-level testing and silicon validation
- Hands-on exposure to debugging (board level & design level)
- Familiarity with Xilinx / Intel toolchains
- Understanding of protocols: PCIe, Ethernet, DDR4/5, Memory
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