Verification Engineering Lead Opportunity
6 days ago
Job Overview
We are seeking a seasoned verification engineer to lead our verification efforts. As the lead, you will be responsible for driving the verification of a block/subsystem or SOC from concept to delivery.
Key Responsibilities:
- Owning and executing the verification plan for a block/subsystem or SOC
- Leading a team of engineers with a proven track record of success
- Extensive experience in IP/sub-system and/or SoC level verification based on SystemVerilog/UVM
- Experience in test plan execution using high-quality constrained random UVM tests to hit coverage goals on time
- Expertise in debugging and all aspects of verification flow including gate-level simulations
- Verification of PCI Express, UCIe, CXL, NVMe, AXI, ACE, CHI, Ethernet, RoCE, RDMADDR, LPDDR, HBM, ARM, and RISC-V CPU-based subsystems/SOCs
- Power-aware simulations using UPF
- Proficiency in EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, and Jasper
- Experience with revision control systems like Git, Perforce, and Clearcase
- Desirable skills include SVA and formal verification, as well as scripting in Python, Perl, or TCL
Requirements:
- 5+ years of hands-on DV experience in System Verilog/UVM
- Proven leadership skills with a track record of leading a team of engineers
- Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM
What We Offer:
- A challenging and rewarding role with opportunities for growth and development
- A dynamic and collaborative work environment
- The chance to work on cutting-edge projects and technologies
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