Lead Digital Design Engineer for High-Speed SerDes Solutions
1 week ago
We are seeking a highly skilled Lead Digital Design Engineer to join our team at Texas Instruments. This is an exciting opportunity to work on the development of new TI SerDes products, leveraging state-of-the-art process technology to solve customers' challenges in the automotive space.
As a key member of our design team, you will be responsible for modeling, designing, and implementing integrated circuits with a focus on high-speed SerDes solutions. You will interface with various engineering teams within the product line, driving flawless execution and finding innovative solutions to customers' problems through out-of-the-box thinking.
Main Responsibilities- Be a key team member from product definition to release to market, working closely with all functions (e.g., systems, analog design, verification, test, applications).
- Define or enhance the micro-architecture for digital blocks/top and design them along with the rest of the team.
- RTL development and verification (RTL and Gate level).
- Collaborate with analog designers on mixed-signal and DSP blocks and interfaces.
- Work closely with the verification team to build the full-chip verification plan, tests. Support functional debugs and RCAs.
- Support silicon validation activities, test program development, and customer engagement and silicon/application debug needs.
- Drive architectural optimization for area, power, and performance improvements for a given node.
- Address performance bottlenecks through micro-architecture.
- Hands-on front-end design experience of complex multi-clock domain blocks.
- Ability to convert high-level system requirements/changes into micro-architectural changes and then into RTL.
- Ability to extract the functionality/micro-architecture of existing designs even with sparse legacy documentation.
- Familiarity with verification environments to actively participate in functional debugs.
- Good knowledge of static timing analysis and constraints debugging.
- Understand and own in detail the functional specifications of IPs/SoC.
- Ensure that design-for-test (DFT) standards are addressed by design.
- Participate in and conduct design reviews. Create necessary design documentation.
- Ability to take initiatives and drive results working with team members across time-zones.
- Handling & owning design deliverables and schedule.
- Bachelor's/Master's in Electrical/Electronics Engineering.
- 3-10 years of relevant experience.
- Excellent RTL design (Verilog) skills including Lint, Simulation, Debug, Synthesis, and LEC (preferably Cadence toolchain).
- Experience in identifying and implementing complex ECOs in netlist.
- Experience in writing and debugging timing constraints at IP/SoC level.
- Experience in silicon functional debug/RCA to map bugs to RTL. Familiarity with Si-bringup & Bench testing.
- Experience in FPGA prototyping of full/parts of system would be a plus.
- Experience in digital signal processing and Matlab modeling would be a plus.
- Understanding of high-speed protocol and interfaces like CSI, DSI, MiPi, HDMI, Display Port etc.
- Knowledge of PLL, SerDes, Encoders, Decoders, Video Compression, Video Encryption, I2C, and SPI.
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