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Design Lead for Memory Controller IP Development
1 week ago
At Cadence Design Systems, we're a team of innovators who tackle complex technical challenges. Our goal is to develop cutting-edge solutions that make a lasting impact on the world of technology.
Job OverviewWe're seeking a highly skilled Senior RTL Design Engineer to join our DDR Memory Controller IP development team. As a key member of this team, you'll be responsible for designing and supporting the RTL of our DDR Memory Controller solution.
The role involves working with existing RTL code, adding new features, ensuring various customer configurations are clean during verification regressions, supporting customers, and guaranteeing the design adheres to LINT and CDC design guidelines.
Responsibilities- Design and support RTL of DDR Memory Controller solution
- Add new features to existing RTL code
- Verify customer configurations and ensure design cleanliness
- Support customers in RTL design and implementation
To succeed in this role, you'll need:
- Bachelor's degree in Electrical Engineering or Electronics and Communications Engineering
- Minimum 2 years of experience as a design and verification engineer with significant work experience in RTL design and development
- Strong understanding of Verilog and System Verilog
- Experience with UVM-based environments and debugging
- Familiarity with AXI3 and AXI4 protocols is a plus
As a member of our team, you'll enjoy a dynamic work environment, opportunities for growth and development, and the chance to work on projects that truly make a difference.