SeniorRTLLead

4 days ago

Bikaner, Rajasthan, India beBeeRtlDeveloper Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
Job Title: Sr RTL Principal Design Engineer", "

Job Description:

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  • Design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution.", "
  • Work involved includes design and addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions.", "
  • Support customers, ensuring design is clean for LINT and CDC design guidelines.", "
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Position Requirements:

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  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with experience as a design and verification engineer.", "
  • 8-16 years of core RTL Design experience using Verilog is a must.", "
  • System Verilog experience and experience with UVM based environment usage/debugging is required.", "
  • PCIe/CXL/IDE experience is needed. Prior experience in implementation of complex protocols is a must.", "
  • Prior experience in IP development teams would be an added advantage.", "
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Scripting knowledge is an advantage.

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