
Senior ASIC/ SOC Designer
21 hours ago
Exciting opportunities exist in ASIC/SOC Verification
We are seeking skilled engineers to join our team in Solapur, India.
Job DescriptionEnd-to-End Power VerificationWe require two experienced engineers with 6 years of experience and one engineer with 4 years of experience. The key skills for this role include power-aware verification using UPF, verification of leakage, sleep, clock tree, and active use cases.
- Power switch coverage analysis
- Clock & reset verification (glitch, freq, spec compliance, multiple paths)
- Strong DV (SystemVerilog, UVM), RTL + GLS with PG netlist
- Understanding of power intent & SoC clock/reset architecture
For this role, we need two engineers with 6 and 4 years of experience respectively. Key skills required include DSP subsystem test case development & performance analysis, processor knowledge (DSP preferred), exposure to Neural Network Engines (NNE), and performance verification methods.
- C-based verification + strong SV/UVM knowledge
We are looking for two experienced engineers with 6 years of experience and one engineer with 2 years of experience. Required skills include end-to-end Debug Subsystem verification, RTL DV, GLS, coverage closure, understanding of ARM CoreSight Debug Architecture, and work with architecture & SW teams for debug requirements.
- Define Verification Plan (VPlan)
- CPU debug system understanding (trace, crash debug)
- Strong SV, UVM, C expertise
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